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[VHDL-FPGA-Verilogfifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序,是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1024 | Author: 夏社 | Hits:

[DSP programFIR2

Description: FIR. 该程序用线性缓冲区和间接寻址方法实现FIR滤波器-FIR. The process by linear buffer and indirect methods of addressing the achievement of FIR filter
Platform: | Size: 1024 | Author: pu | Hits:

[VHDL-FPGA-Verilogfifo89

Description: 先进先出FIFO缓冲器,8位字宽,9位字深,很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
Platform: | Size: 269312 | Author: gdfrg | Hits:

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